January JEDEC. STANDARD. DDR2 SDRAM SPECIFICATION be addressed to JEDEC Solid State Technology Association, Wilson Boulevard. DDR2 SDRAM is a double data rate synchronous dynamic random-access memory interface. It superseded the original DDR SDRAM specification, and is superseded by .. JEDEC standard: DDR2 SDRAM Specification: JESDF, November ** ยท JEDEC. The JEDEC memory standards are the specifications for semiconductor memory circuits and Memory modules of the DDR2-SDRAM type are available for laptop, desktop, and server computers in a wide selection of capacities and access.

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Archived from the original on These chips are mostly standard DDR chips that have been tested and rated to be capable of operation at higher clock rates by the manufacturer. Retrieved August 25, Both performed worse than the original DDR specification due to higher latency, which made total access times longer.

However, latency is greatly increased as a trade-off. DDR2 was introduced in the second quarter of at two initial clock rates: DDR2 started to become competitive against the older DDR standard by the end ofas modules with lower latencies became available.

This page was last edited on 2 Augustat In addition to double pumping the data bus as in DDR SDRAM transferring data on the rising and falling edges of the bus clock signalDDR2 allows higher bus speed and requires lower power by running the internal clock at half the speed of the data bus.

The documentation of modern memory modules, such as the standards for the memory ICs [4] and a reference design of the module [5] requires over one hundred pages. In other projects Wikimedia Commons. The specification notes that these prefixes are included in the document only to reflect common usage. These chips cannot achieve the clock rates of GDDR3 but are inexpensive and fast enough to be used as memory on mid-range cards.



The definitions of kilo, giga, and mega based on powers of two are included only to reflect common usage. The two factors combine to produce a total of four data transfers per internal clock cycle. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally.

The document further refers to the description of the IEC binary prefixes in Amendment 2 of IEC”Letter symbols to be used in electrical technology”for an alternate system of prefixes [notes 1] and includes a table of the IEC prefixes in the note. The document notes that these prefixes are used in their decimal sense for serial communication data rates measured in bits.

At least one manufacturer has reported this reflects successful testing at a higher-than-standard data rate [4] whilst others simply round up for the name. This page was last edited on 11 Januaryat This packaging change was necessary to maintain signal integrity at higher bus speeds.

DDR2’s bus frequency is boosted by electrical interface improvements, on-die terminationprefetch buffers and off-chip drivers.

This committee consists of members from manufacturers of microprocessors, memory ICs, memory modules, and other components, as well as component integrators, such as video card and personal computer makers. Dynamic random-access memory DRAM.

Please update this article to reflect recent events or newly available information. Retrieved from ” https: This article needs to be updated. It had severe overheating issues due to the nominal DDR voltages. Wikipedia articles in need of updating from January All Wikipedia articles in specificaiton of updating.

JEDEC memory standards

This is because DDR2 memory modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this spceification to 8 bytes of data per transfer.


These cards actually use standard DDR2 chips designed for use as main system memory although operating with higher latencies to achieve higher clockrates.

The specification contains definitions of the commonly used prefixes kilomegaspeciifcation giga usually combined with the units byte and bit to designate multiples of the units. The purpose of the standard is to promote the uniform use of symbols, abbreviations, terms, and definitions throughout the semiconductor industry. The specification defines the two common units of information: Alternatively, DDR2 memory operating at twice the external data dd2 clock rate as DDR may provide twice the bandwidth with the same latency.


Power savings are achieved primarily due to an improved manufacturing process through die shrinkage, resulting in a drop in operating voltage 1. The standards specify memory module label formats for end-user markets. From Wikipedia, the free encyclopedia. During an access, four bits were read or written to or from a four-bit-deep prefetch queue. The standards specify the physical and electrical characteristics of the modules, and include the data for computer simulations of the memory module operating in a system.

JEDEC memory standards – Wikipedia

Views Read Edit View history. The lower memory clock frequency may also enable power reductions in applications that do not require the highest available data rates.

By using this site, you agree to the Terms of Use and Privacy Policy. Such chips draw significantly more power than slower-clocked chips, but usually offered little or no improvement in real-world performance.

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